High SCR design for one-transistor split-gate full featured EEPROM

IEEE Electron Device Letters

Volumn 25, Issue 7, 2004, Pages 498-500

  Chu, Wen Ting ^a   Lin, Hao Hsiung ^a   Wang, Yu Hsiung ^b   Hsieh, Chia Ta ^b   Sung, Hung Cheng ^b   Lin, Yung Tao ^b   Wang, Chung S ^b  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; DRY ETCHING; ELECTRIC POTENTIAL; ELECTRON TUNNELING; PHOTOLITHOGRAPHY; POLYSILICON; SILICON NITRIDE; SMART CARDS; TRANSISTORS;

FOWLER-NORDHEIM TUNNELING; FULL FEATURED EEPROM; PROGRAM ERASE CYCLING TEST; SOURCE COUPLING RATIO; SPLIT GATE CELL;

PROM;

EID: 3342964427     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.830277     Document Type: Article

References (10)

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