Study of 90-nm MOSFET subthreshold hump characteristics using newly developed MOSFET array test structure

IEEE Transactions on Semiconductor Manufacturing

Volumn 19, Issue 1, 2006, Pages 19-26

  Mizumura, Akira ^a,b   Oishi, Tetsuya ^a   Yokoyama, Nobuhiko ^a   Nonaka, Mie ^a   Tanaka, Shigeyuki ^a   Ammo, Hiroaki ^a  

^a SONY CORPORATION   (Japan)

^b Institute of Electronics   (Japan)

Author keywords

MOSFET array; Off leakage current; Sub threshold hump; Threshold voltage; Variation

Indexed keywords

GATE LEAKAGE; HUMP VARIATION; SUBTHRESHOLD SLOPE;

CURRENT DENSITY; GATES (TRANSISTOR); LEAKAGE CURRENTS; LSI CIRCUITS; MICROPROCESSOR CHIPS; POLYSILICON; SILICON WAFERS;

MOSFET DEVICES;

EID: 33144477366     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2005.863257     Document Type: Conference Paper

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