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Volumn , Issue , 2002, Pages 276-283

System on programmable chip for real-time control implementations

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GENERAL PURPOSE COMPUTERS; INTERFACES (COMPUTER); RECONFIGURABLE HARDWARE;

EID: 32844456105     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2002.1188692     Document Type: Conference Paper
Times cited : (7)

References (7)
  • 2
    • 0026242764 scopus 로고
    • PACE: A regular array for implementing regularly and irregularly structured algorithms
    • Spray, A. and S. Jones (1991). PACE: A regular array for implementing regularly and irregularly structured algorithms. IEE Proceedings-G, 138, pp. 613-619.
    • (1991) IEE Proceedings-G , vol.138 , pp. 613-619
    • Spray, A.1    Jones, S.2
  • 3
    • 0032108127 scopus 로고    scopus 로고
    • Targeted processor architectures for high-performance controller implementation
    • Jones, S., R. Goodall and M. Gooch (1998). Targeted processor architectures for high-performance controller implementation. Control Engineering Practice 6., pp. 867-878
    • (1998) Control Engineering Practice , vol.6 , pp. 867-878
    • Jones, S.1    Goodall, R.2    Gooch, M.3
  • 4
    • 0027611957 scopus 로고
    • Very high sample rate digital filters using the δ operator
    • Goodall, R. M. and B. Donaghue (1993). Very high sample rate digital filters using the δ operator. Proceedings IEE-G, Pt G, 140, pp. 199-206.
    • (1993) Proceedings IEE-G , vol.140 , pp. 199-206
    • Goodall, R.M.1    Donaghue, B.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.