Targeted processor architectures for high-performance controller implementation

Control Engineering Practice

Volumn 6, Issue 7, 1998, Pages 867-878

  Jones, Simon ^a   Goodall, Roger ^a   Gooch, Mark ^a  

^a LOUGHBOROUGH UNIVERSITY   (United Kingdom)

Author keywords

Architectures; Arithmetic and logic units; Control algorithms; Control applications; Hardware

Indexed keywords

ALGORITHMS; CONTROL SYSTEM SYNTHESIS; DIGITAL SIGNAL PROCESSING;

LINEAR TIME-INVARIANT CONTROLLERS;

LINEAR CONTROL SYSTEMS;

EID: 0032108127     PISSN: 09670661     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0967-0661(98)00074-4     Document Type: Article

References (12)

1. Catthoor, F., Franssen, F., Cools, K., Hendriks, C., Demeester, F., De Schutter, J., & De Man, H. (1991). An application-specific microcoded architecture for a robot control application. In: H. S. Moscovitz, & K. Yao, (Eds.), VLSI signal processing IV (pp. 452-461). New York: IEEE press.
2. Chen, D.C., & Rabaey, J. (1991). PADDI: Programmable arithmetic devices for digital signal processing. In: H. S. Moscovitz, & K. Yao, (Eds.), VLSI signal processing IV (pp. 240-249). New York: IEEE press.
3. Forsythe, W., & Goodall, R.M. (1991). Digital Control. Basingstoke: Macmillan Education Ltd.
4. Fujioka, Y., Kameyama, M., & Tomabechi, N. (1996). Reconfigurable parallel VLSI processor for dynamic control of intelligent robots. IEE Proceedings - Computers and Digital Techniques, 143, 23-29.
5. Garcia Nocetti, D.F., & Fleming, P.J. (1992). Parallel processing in digital control. London: Springer.
6. Goodall, R.M., & Donoghue, B.J. (1993). Very high sample rate digital filters using the δ operator. IEE Proceedings-G, 140, 199-206.
7. Grout, I.A., Burge, S.E., & Dorey, A.P. (1995). Design and testing of a PI controller ASIC. Microprocessors and Microsystems, 19, 15-22.
8. Jaswa, V.C., Thomas, C.E., & Pedicone, J. (1985). CPAC: Concurrent processor architecture for control. IEEE Transactions on Computers, C-34, 163-169.
9. Lang, J.H. (1984). On the design of a special-purpose digital control processor. IEEE Transactions on Automatic Control, AC-29, 195-201.
10. Sadayappan, P., Ling, Y-L.C., Olson, K.W., & Orin, D.E. (1989). A restructurable VLSI robotics vector processor architecture for real-time control. IEEE Transactions on Robotics and Automation, 5, 583-599.
11. Spray, A., & Jones, S. (1991). PACE: A regular array for implementing regularly and irregularly structured algorithms. IEE Proceedings-G, 138, 613-619.
12. Tsunekawa, Y., & Miura, M. (1995). High performance VLSI architecture suitable for control-systems for state-space digital filters using distributed arithmetic. Electronics and Communications in Japan, 5, 12-21.