Double-residue modular range reduction for floating-point hardware implementations

IEEE Transactions on Computers

Volumn 55, Issue 3, 2006, Pages 254-267

  Villalba, Julio ^a   Lang, Tomas ^b   Gonzalez, Mario A ^a  

^a UNIVERSITY OF MÁLAGA   (Spain)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Elementary function evaluation; Floating point arithmetic; Range reduction

Indexed keywords

COMPUTATION THEORY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DIGITAL ARITHMETIC; ESTIMATION; ITERATIVE METHODS;

ELEMENTARY FUNCTION EVALUATION; HARDWARE IMPLEMENTATIONS; MODULAR RANGE REDUCTION ALGORITHM; RANGE-REDUCTION;

ALGORITHMS;

EID: 32044440559     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2006.38     Document Type: Article

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