Confirmation of electric properties of traps at silicon-on-insulator (SOI)/buried oxide (BOX) interface by three-dimensional device simulation

Physica E: Low-Dimensional Systems and Nanostructures

Volumn 24, Issue 1-2 SPEC. ISS., 2004, Pages 92-95

  Nakajima, Y ^a   Sasaki, K ^a   Hanajiri, T ^a   Toyabe, T ^a   Morikawa, T ^a   Sugano, T ^a  

^a TOYO UNIVERSITY   (Japan)

Author keywords

Kink effect; SOI; Surface recombination velocity; Trap

Indexed keywords

ELECTRON ENERGY LEVELS; ELECTRON TRAPS; INTERFACES (MATERIALS); MOSFET DEVICES; SILICON WAFERS; SUBSTRATES;

KINK EFFECT; SOI; SURFACE RECOMBINATION VELOCITY;

SILICON ON INSULATOR TECHNOLOGY;

EID: 3142766864     PISSN: 13869477     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.physe.2004.04.031     Document Type: Conference Paper

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