Double pass-transistor logic for high performance wave pipeline circuits

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1998, Pages 495-500

  Parthasarathy, Rajesh S ^a   Sridhar, Ramalingam ^a  

^a UNIVERSITY AT BUFFALO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; LOGIC DESIGN; LOGIC GATES; TUNING;

DELAY BALANCING; DOUBLE PASS TRANSISTOR LOGIC (DPL) GATES; WAVE PIPELINE CIRCUITS;

LOGIC CIRCUITS;

EID: 0031706884     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)