A CMOS macro-model for MTJ resistor of MRAM cell

Physica Status Solidi (A) Applied Research

Volumn 201, Issue 8, 2004, Pages 1653-1657

  Cho, Chung Hyun ^a   Ko, Ju Hyun ^a   Kim, Daejeong ^a  

^a Kookmin University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC RESISTANCE; ELECTRICAL ENGINEERING; MAGNETIZATION; MAGNETORESISTANCE; MATHEMATICAL MODELS; RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE; TRANSISTORS;

BIT LINE (BL); GATE VOLTAGES; MAGNETIC LAYERS; OPERATING VOLTAGES;

RESISTORS;

EID: 3142747696     PISSN: 00318965     EISSN: None     Source Type: Journal    
DOI: 10.1002/pssa.200304613     Document Type: Conference Paper

References (2)

1. S. Tehrani, B. Engel, J. M. Slaughter, E. Chen, M. DeHerrera, M. Durlan, P. Naji, R. Whig, J. Janesky, and J. Calder, IEEE Trans. Magn. 36, 2752 (2000).
2. H. S. Jeong, G. H. Koh, I. H. Song, W. J. Park, T. W. Kim, S. J. Jeong, T. N. Hwang, S. J. Ahn, H. J. Kim, J. S. Hong, W. C. Jeong, S. H. Lee, J. H. Park, W. Y. Cho, J. S. Kim, S. H. Song, H. J. Kim, S. O. Park, U. I. Jeong, and K. Kim, IEEE IEDM. 551 (2002).