Demystifying design-for-yield

Semiconductor International

Volumn 27, Issue 8, 2004, Pages 42-51+158

  Peters, Laura ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; DEFECTS; DIELECTRIC MATERIALS; ENERGY UTILIZATION; INVESTMENTS; LEAKAGE CURRENTS; LITHOGRAPHY; LSI CIRCUITS; MICROPROCESSOR CHIPS; PRODUCT DESIGN; SHRINKAGE; TRANSISTORS;

DESIGN-FOR-MANUFACTURABILITY (DFM); DESIGN-FOR-TEST (DFT); DESIGN-FOR-YIELD (DFY); INTERCONNECT DELAYS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 3142658622     PISSN: 01633767     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (3)

1. R.C. Leachman and C.N. Berglund, "Systematic Mechanisms Limited Yield (SMLY) Assessment Study," International SEMATECH, Doc. #03034382A-ENG, March 2003.
2. C.N. Berglund, "Trends in Systematic Non-Particle Yield Loss Mechanisms and the Implication for IC Design," Proc. SPIE, Vol. 5042, Design and Process Integration for Microelectronic Manufacturing II, February 2003, p. 395.
3. M. Okazaki, et al., '"Sea of Kelvin' Multiple-Pattern Arrangement Interconnect Characterization...," IEEE IITC, June 2004, p. 211.