Thermal performance impacts of heat spreading lids on flip chip packages: With and without heat sinks

Microelectronics Reliability

Volumn 46, Issue 2-4, 2006, Pages 380-385

  Wakil, Jamil ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC RESISTANCE; HEAT SINKS; MECHANICAL PROPERTIES; SURFACE CHEMISTRY; THERMOANALYSIS; WIND TUNNELS;

CFD MODELS; DIRECT LID ATTACH (DLA); HIGHER MODULE COSTS; MECHANICAL ADVANTAGES;

CHIP SCALE PACKAGES;

EID: 30844434577     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2005.01.007     Document Type: Article

References (9)

1. Ando H, Kikuchi H, Sato T. Flip-chip package with a heat spreader for high power dissipation LSI chips. In: Proceedings, 1999 Electronic Components and Technology Conference. p. 227-31.
2. Starr O et al. Heat spreader attach: a microprocessor thermal solution. In: Proceedings, 1999 Electronic Components and Technology Conference. p. 238-42.
3. T. Lee An investigation of thermal enhancement on flip chip BGA Packages using CFD tool IEEE Trans Comput Packag Technol 23 3 2000 481 489
4. Dolbear TP, Tarter T. Thermal management of pin grid array packaging for flip chip connected X86 microprocessors. In: Proceedings, 1997 International Systems Packaging and Symposium. p. 279-84.
5. JESD51-9, EIA/JEDEC Standard 51-9. Test boards for area array surface mount package thermal measurements, July 2000.
6. JESD51-6, EIA/JEDEC Standard 51-6. Integrated circuits thermal test method environmental conditions-forced convection (moving air), March 1999.
7. JESD51-2, EIA/JEDEC Standard 51-2. Integrated circuits thermal test method environmental conditions-natural convection (still air), December 1995.
8. R. Panton Incompressible flow 1996 John Wiley New York p. 129-46
9. Wakil J, Sathe S. Comparison of IBM Endicott thermal test plenum to the JEDEC Standards for natural and forced convection testing. IBM Confidential Technical Paper, 2001.