Efficient instruction-level optimization methodology for low-power embedded systems

Proceedings of the International Symposium on System Synthesis

Volumn , Issue , 2001, Pages 147-152

  Choi, K W ^a   Chatterjee, A ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ENERGY DISSIPATION; MATHEMATICAL MODELS; PROBLEM SOLVING; SIMULATED ANNEALING; TRAVELING SALESMAN PROBLEM; TREES (MATHEMATICS);

POWER CONSUMPTION;

EMBEDDED SYSTEMS;

EID: 0034795908     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/500001.500035     Document Type: Conference Paper

References (15)

1. Code restructuring for improving execution efficiency, code size and power consumption for embedded DSPs
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3. Instruction level power analysis and optimization of software
4. Compilation techniques for low energy: An overview
5. Instruction scheduling to reduce switching activity of off-chip busses for low-power systems with caches
6. Compiler optimization on instruction scheduling for low power
7. Software design for low power
8. Low power architecture design and compilation techniques for high-performance processors
9. Incorporating speculative execution into scheduling of control-flow-intensive designs
10. Shortest connection networks and some generalizations
11. Energy efficient CMOS microprocessor design