Memory fault modeling trends: A case study

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 20, Issue 3, 2004, Pages 245-255

  Hamdioui, Said ^a,b   Wadsworth, Rob ^c   Delos Reyes, John ^b   Van De Goor, Ad J ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b INTEL CORPORATION   (United States)

^c STMICROELECTRONICS   (France)

Author keywords

Data backgrounds; Dynamic faults; Fault coverage; Fault models; Memory tests; Static faults

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; EMBEDDED SYSTEMS; MATHEMATICAL MODELS; MICROELECTRONICS; STATIC RANDOM ACCESS STORAGE;

DATA BACKGROUNDS; DYNAMIC FAULTS; FAULT COVERAGE; FAULT MODELS; MEMORY TESTS; STATIC FAULTS;

SEMICONDUCTOR DEVICE TESTING;

EID: 3042845297     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/B:JETT.0000029458.57095.bb     Document Type: Article

References (20)

1. M.S. Abadir and J.K. Reghbati, "Functional Testing of Semiconductor Random Access Memories," ACM Computer Surveys, vol. 15, no. 3, pp. 175-198, 1983.
2. R.D. Adams, "High Performance Memory Testing, Kluwer Academic Publisher, ISBN: 1-4020-7255-4, 2003.
3. Z. Al-Ars and Ad J. van de Goor, "Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs," Proc. of Design Automation and Test in Europe, 2001, pp. 496-503.
4. Z. Al-Ars and A.J. van de Goor, "Approximating Infinite Dynamic Behavior for DRAM Cell Defects," Proc. IEEE VLSI Test Symp., 2002, pp. 401-406.
5. Allan et al., "2001 International Technology Roadmap for Semiconductors," Computer, vol. 35, no. 1, pp. 42-53, 2002.
6. M.A. Breuer and A.D. Friedman, Diagnosis and Reliable Design of Digital Systems, Woodland Hills, CA, USA: Computer Science Press, 1976.
7. R. Dekker et al., "A Realistic Fault Model and Test Algorithms for Static Random Access Memories," IEEE Trans. on Computers, vol. C9, no. 6, pp. 567-572, 1990.
8. J.H. De Jonge and A.J. Smeulders, "Moving Inversions Test Pattern is Thorough, Yet Speedy," Comp. Design, 1976, pp. 169-173.
9. S. Hamdioui and A.J. van de Goor, "Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests," Proc. of Ninth Asian Test Symposium, 2000, pp. 131-138.
10. S. Hamdioui, Z. Al-Ars, and A.J. van de Goor, "Testing Static and Dynamic Faults in Random Access Memories," Proc. of IEEE VLSI Test Symposium, 2002, pp. 395-400.
11. S. Hamdioui, A.J. van de Goor, and M. Rodgers, " March SS: A Test for All Static Simple RAM Faults," Proc. IEEE international Workshopon Memory Technology, Design, and Testing, 2002, pp. 95-100.
12. S. Hamdioui, Z. Al-ars, A.J. van de Goor, and M. Rodgers, "Dynamic Faults in Random Access Memories: Concept, Fault Models and Tests," Journal of Electronic Testing, Theory and Application, vol. 19, no. 2, pp. 195-205, 2003.
13. V.K. Kim and T. Chen, "On Comparing Functional Fault Coverage and Defect Coverage for Memory Testing," IEEE Trans. on CAD, vol. 18, no. 11, pp. 1676-1683, 1999.
14. M. Marinescu, "Simple and Efficient Algorithms for Functional RAM Testing," in Proc. of International Test Conference, 1982, pp. 236-239.
15. S. Naik et al., "Failure Analysis of High Density CMOS SRAMs," IEEE Design and Test of Computers, vol. 10, no. 1, pp. 13-23, 1993.
16. R. Nair, "An Optimal Algorithm for Testing Stuck-at Faults Random Access Memories," IEEE Trans. on Comp., vol. C-28, no. 3, pp. 258-261, 1979.
17. D.S. Suk and S.M. Reddy, "A March Test for Functional Faults in Semiconductors Random-Access Memories," IEEE Trans. on Comp., vol. C-30, no. 12, pp. 982-985, 1981.
18. A.J. van de Goor, Testing Semiconductor Memories, Theory and Practice, ComTex Publishing, Gouda, The Netherlands, 1998.
19. A.J. van de Goor and J. de Neef, "Industrial Evaluation of DRAMs Tests," Proc. of Design Automation and Test in Europe, 1999. pp. 623-630.
20. A.J. van de Goor and Z. Al-Ars, "Functional Fault Models: A Formal Notation and Taxonomy," Proc. of IEEE VLSI Test Symposium, 2000, pp. 281-289.