Design and modelling of a voltage controlled N-well resistor using the MOS tunneling diode structure

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 2002, Pages 1123-1126

  Kammerer, Jean Buptiste ^a   Hebrard, Luc ^a   Frick, Vincent ^a   Poure, Philippe ^a   Braun, Francis ^a  

^a CENTRE DE CALCUL DE L INSTITUT NATIONAL DE PHYSIQUE NUCLEAIRE ET DE PHYSIQUE DES PARTICULES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ABSOLUTE VALUES; ANALOG DESCRIPTION LANGUAGE; CMOS PROCESSS; COMPACT MODEL; DEVICE RESISTANCE; M-TECHNOLOGIES; MOS TUNNELING; N-WELL RESISTOR; POLYSILICON RESISTORS; PROCESS DISPERSION; SILICON AREA; STANDARD CMOS TECHNOLOGY; TUNING RANGES; VHDL-AMS; VOLTAGE CONTROLLED RESISTORS; VOLTAGE-CONTROLLED;

CMOS INTEGRATED CIRCUITS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; HIGH LEVEL LANGUAGES; POLYSILICON; RESISTORS; TUNNEL DIODES;

PROCESS CONTROL;

EID: 3042816503     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2002.1046449     Document Type: Conference Paper

References (6)

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