A scalable instruction buffer and align unit for xDSPcore

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 7, 2004, Pages 1094-1100

  Panis, Christian ^a   Grünbacher, Herbert ^a   Nurmi, Jari ^b  

^a Carinthia Tech Institute   (Austria)

^b TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

Application specific integrated circuits (ASICs); Buffer memories; Cache memories; Digital signal processors; Parallel architectures; Reduced instruction set computing

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; PROBLEM SOLVING; REDUCED INSTRUCTION SET COMPUTING; SOFTWARE ENGINEERING; VERY LONG INSTRUCTION WORD ARCHITECTURE;

BUFFER MEMORIES; CORE PERFORMANCE; DIGITAL SIGNAL PROCESSORS (DSP); PARALLEL ARCHITECTURES;

BUFFER STORAGE;

EID: 3042745238     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.829411     Document Type: Conference Paper

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