Cooperative software multithreading to enhance utilization of embedded processors for network applications

Proceedings - Euromicro Conference on Parellel, Distribeted and Network-based Proceeding

Volumn , Issue , 2004, Pages 300-307

  Albrecht, Carsten ^a   Hagenau, Rainer ^a   Döring, Andreas ^b  

^a UNIVERSITY OF LÜBECK   (Germany)

^b IBM RESEARCH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

DIRECT MEMORY ACCESS (DMA); EMBEDDED PROCESSORS; INSTRUCTION SET ARCHITECTURES (ISA); MEMORY MANAGEMENT UNITS (MMU);

CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA STORAGE EQUIPMENT; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; PROGRAM PROCESSORS;

EMBEDDED SYSTEMS;

EID: 3042670307     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EMPDP.2004.1271459     Document Type: Conference Paper

References (15)

1. A. Agarwal. Performance Tradeoffs in Multithreaded Processors. IEEE Transactions on Parallel and Distributed Systems, 3(5):525-539, 1992.
2. A. V. Aho, R. Sethi, and J. D. Ullman. Compilers, Principles, Techniques, and Tools. Addison-Wesley Publishing Company, 1985.
3. C. Albrecht. Reduction and Shaping of Context Data for Cooperative Multitasking. Master's thesis, University of Lübeck, Germany, June 2002.
4. C. J. Beckmann. Hardware and Software for Functional and Fine Grain Parallelism. PhD thesis, University of Illinois at Urbana-Champaign, 1993.
5. T. Halfhill. Intel Network Processor Target Routers - IXP1200 Integrates Seven Cores for Multithreaded Packet Routing. Microprocessor Report, 13(12), 1999.
6. IBM Microelectronics Division. PowerNP NPe405H Network Processor User's Manual, 2002.
7. K. Krewell. Rainier Leads PowerNP Family - IBM's Chip Handles OC48 Today With a Clear Channel to OC192. Microprocessor Report, 15(1):10-12, 2001.
8. Motorola Semiconductors. MPC8260 PowerQUICC II Microcodes, 2002.
9. Motorola Semiconductors. MPC8260 PowerQUICC II User's Manual and MPC8280 PowerQUICC II Specification Addendum to the MPC8260 PowerQUICC II User's Manual, 2002.
10. S. S. Muchnick. Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers, 1997.
11. R. Muth. Register Liveness Analysis of Executable Code. PhD thesis, Dept. of Computer Science, University of Arizona, Dec. 1998.
12. E. Rohou, F. Bodin, A. Seznec, G. Le Fol, F. Charot, and F. Raimbault. System for Assembly-Language Transformation and Optimization. Technical Report 2980, INRIA, 1996.
13. J. S. Snyder, D. B. Whalley, and T. P. Baker. Fast Context Switches: Compiler and Architectural Support for Preemptive Scheduling. Microprocessors and Microsystems, pages 35-42, 1995.
14. J. Wagner and R. Leupers. C Compiler Design for an Industrial Network Processor. In Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, pages 155-164. ACM Press, 2001.
15. C. A. Waldspurger and W. E. Weihl. Register Relocation: Flexible Contexts for Multithreading. In Proceedings of the 20th Annual International Symposium on Computer Architecture, pages 120-130, San Diego, CA, USA, 1993.