Characterization & modeling of low electric field gate-induced-drain- leakage

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2004, Pages 149-154

  Rideau, D ^a   Dray, A ^a   Gilibert, F ^a   Agut, F ^a   Giguerre, L ^b   Gouget, G ^a   Minondo, M ^a   Juge, A ^a  

^a STMICROELECTRONICS   (France)

^b PHILIPS RESEARCH LABORATORIES   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC FIELDS; ELECTRIC POTENTIAL; ELECTRON TUNNELING; MATHEMATICAL MODELS; SEMICONDUCTOR JUNCTIONS;

DRAIN VOLTAGE; GATE INDUCED DRAIN LEAKAGE (GIDL); TRAP-ASSISTED TUNNELING;

LEAKAGE CURRENTS;

EID: 3042661896     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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