Tolerating late memory traps in dynamically scheduled processors

IEEE Transactions on Computers

Volumn 53, Issue 6, 2004, Pages 732-743

  Qiu, Xiaogang ^a   Dubois, Michel ^b  

^a SUN MICROSYSTEMS   (United States)

^b University of Southern California   (United States)

Author keywords

Exception; Instruction level parallelism; Memory consistency model; Memory system; Microarchitecture; Prefetching; Simulations; Trap

Indexed keywords

CACHE MEMORY; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; VIRTUAL REALITY;

DYNAMICALLY SCHEDULED PROCESSORS; INSTRUCTION LEVEL PARALLELISM; LATE MEMORY TRAPS; MEMORY CONSISTENCY;

PARALLEL PROCESSING SYSTEMS;

EID: 3042629361     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2004.18     Document Type: Article

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