Technology scaling of critical charges in storage circuits based on cross-coupled inverter-pairs

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2004, Pages 675-676

  Heijmen, Tino ^a   Kruseman, Bram ^a   Van Veen, Rutger ^a   Meijer, Maurice ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

Critical charge; Flip flops; Soft errors; SRAM cells; Technology scaling

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ENERGY TRANSFER; FLIP FLOP CIRCUITS; LOGIC GATES; TRANSISTORS;

CRITICAL CHARGES; SOFT ERRORS; TECHNOLOGY SCALING;

STATIC RANDOM ACCESS STORAGE;

EID: 3042568659     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. P. Hazucha and Ch. Svensson, "Impact of CMOS Technology Scaling on the Atmospheric Neutron Soft Error Rate," IEEE Trans. Nucl. Sci., Vol. 47, No. 6, Dec. 2000, pp. 2586-2594.
2. R. Baumann, "The Impact of Technology Scaling on Soft Error Rate Performance and Limits to the Efficacy of Error Correction," in Proc. IEEE Int. Dev. Meet. (IEDM), pp. 329-332, 2002.
3. L.B. Freeman, "Critical Charge Calculations for a Bipolar SRAM Array," IBM J. Res. Dev., Vol. 40, No. 1, Jan. 1996, pp. 119-129.