An asynchronous synthesis toolset using Verilog

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 724-725

  Burns, Frank ^a   Shang, Delong ^a   Koelmans, Albert ^a   Yakovlev, Alex ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL CIRCUITS; LOGIC SYNTHESIS; SIGNAL TRANSITION GRAPHS; ASYNCHRONOUS CIRCUITS; INTERMEDIATE FORMATS; LOGIC OPTIMIZATION; NOVEL INTERMEDIATES; OPTIMIZATION TOOLS; SPEED-INDEPENDENT; SPEED-INDEPENDENT CIRCUITS;

GRAPH THEORY; NETWORKS (CIRCUITS); OPTIMIZATION; PETRI NETS; PROBLEM SOLVING; SCHEDULING; SIGNAL PROCESSING; COMPUTER AIDED DESIGN; EXHIBITIONS; TOOLS;

COMPUTER AIDED DESIGN; ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 3042558172     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268948     Document Type: Conference Paper

References (4)

1. A. Bardsley and D. Edwards, Compiling the language Balsa to delay-insensitive hardware, Hardware Description Languages and their Applications (CHDL), pages 89-91, 1997.
2. I. Blunno and L. Lavagno. Automated synthesis of micropipelines from behavioral Verilog HDL, Proc. of IEEE Symp. on Adv. Res. in Async. Cir. and Syst. (ASYNC2000), pp. 84-92.
3. P. Eles, K. Kuchcinski and Z. Peng, System Synthesis with VHDL, Kluwer Academic Publishers, P.O. Box 17,3300 AA Dordrecht, The Netherlands, 1998.
4. D. Shang, F. Xia and A. Yakovlev. "Asynchronous Circuit Synthesis via Direct Translation", ISCAS 2002, IEEE International Symposium on Circuits and Systems, May 2002.