Digital ground bounce reduction by phase modulation of the clock

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 88-93

  Badaroglu, Mustafa ^a,b   Wambacq, Piet ^a   Van Der Plas, Geert ^a   Donnay, Stéphane ^a   Gielen, Georges ^b   De Man, Hugo ^a,b  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITRY; DATA CONVERTERS; GROUND BOUNCE; SWITCHING SPEED; ANALOGUE CIRCUITRY; CHIP SUBSTRATES; CMOS TECHNOLOGY; DIGITAL SWITCHING NOISE; LOW-NOISE DESIGNS; SOC INTEGRATION; SWITCHING ACTIVITIES; SYNCHRONOUS DIGITAL SYSTEM;

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; ELECTRIC CURRENTS; ELECTRIC IMPEDANCE; MICROPROCESSOR CHIPS; PHASE MODULATION; RESONANCE; SIGNAL TO NOISE RATIO; SWITCHING; TRANSFER FUNCTIONS; WAVEFORM ANALYSIS; DESIGN; EXHIBITIONS;

ELECTRIC CLOCKS; CLOCKS;

EID: 3042520967     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268832     Document Type: Conference Paper

References (9)

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