A versatile high speed bit error rate testing scheme

Proceedings - 5th International Symposium on Quality Electronic Design, ISQUED 2004

Volumn , Issue , 2004, Pages 395-400

  Fan, Yongquan ^a   Zilic, Zeljko ^a   Chiang, Man Wah ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CHANNEL CAPACITY; COMPUTATIONAL METHODS; DIGITAL COMMUNICATION SYSTEMS; ELECTRIC CLOCKS; FIELD PROGRAMMABLE GATE ARRAYS; INTERFACES (MATERIALS); OPTICAL FIBERS; SIGNAL TO NOISE RATIO;

BLOCK DIAGRAMS; CLOCK DATA RECOVERY (CDR); PSEUDO RANDOM BIT SEQUENCES (PRBS); TRANSMISSION ERRORS;

BIT ERROR RATE;

EID: 2942696344     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/isqed.2004.1283706     Document Type: Conference Paper

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