Innovate or perish: FPGA physical design

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2004, Pages 148-155

  Taghavi, Taraneh ^a   Ghiasi, Soheil ^a   Ranjan, Abhishek ^b   Raje, Salil ^b   Sarrafzadeh, Majid ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b HierDesign Inc

Author keywords

Delay Estimation; Floorplanning; FPGA; Partitioning; Physical Design; Placement; Routing Architecture

Indexed keywords

DELAY ESTIMATION; FLOORPLANNING; PARTITIONING; PHYSICAL DESIGN; ROUTING ARCHITECTURE;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; HIERARCHICAL SYSTEMS; PROBLEM SOLVING; ROUTERS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 2942674450     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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