The effect of the degree of multistage interconnection networks on their performance: The case of delta and over-sized delta networks

Proceedings - Euromicro Conference on Parellel, Distribeted and Network-based Proceeding

Volumn , Issue , 2004, Pages 72-78

  Aljundi, Ahmad Chadi ^a   Dekeyser, Jean Luc ^a  

^a UNIV LILLE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CROSSBARS; DELTA NETWORKS; SWITCHING ELEMENTS (SE);

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; PARALLEL PROCESSING SYSTEMS; ROUTERS;

INTERCONNECTION NETWORKS;

EID: 2942632026     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EMPDP.2004.1271430     Document Type: Conference Paper

References (24)

1. A. C. Aljundi, J.-L. Dekeyser, M.-T. Kechadi, and I. D. Scherson. Comparative simulations and performance evaluation of mcrb networks using multidimensional queue management. In Proc. Int'l Symp. on Performance Evaluation of Computer and Telecommunication Systems, pages 288-296, San Diego, USA, July 2002.
2. A. C. Aljundi, J.-L. Dekeyser, M.-T. Kechadi, and I. D. Scherson. A study of an evaluation methodology for unbuffered multistage interconnection networks. In Proceedings of 17th International Parallel and Distributed Processing Symposium, IPDPS'03, Nice, France, April 2003.
3. A. C. Aljundi, J. L. Dekeyser, and I. D. Scherson. An interconnection networks comparative performance evaluation methodology: Delta and over-sized delta networks. In Proc. of the 16th International Conference on Parallel and Distributed Computing Systems, pages 1-8, Reno NY., USA, Aug. 2003.
4. S. Cheemalavagu and M. Malek. Analysis and simulation of banyan interconnection networks with 2×2, 4×4 and 8×8 switching elements. In Proc. Real-Time Syst. Symp., pages 83-89, 1982.
5. C. Clos. A study of non-blocking switching networks. Bell system tech. journal, 32(2):406-424, Mar. 1953.
6. D. E. Culler, J. P. Singh, and A. Gupta. Parallel Computer Architecture (A Hardware/Software Approch), chapter Interconnection Network Design. Morgan Kaufmann Publishers, 1999.
7. G. Goke and G. Lipovski. Banyan networks for partitioning multiprocessor systems. In Proc. 1st Annu. Symp. Comput. Arch., pages 21-28, 1973.
8. A. Gottlieb. An overview of the nyu ultracomputer project. Technical report, The NYU Ultracomputer project, Oct. 1987.
9. K. Hwang and F. Briggs. Computer Architecture and Parallel Processing, 5th printing. McGraw-Hill series in computer organization and architecture. McGraw-Hill International Editions, 1989.
10. M. T. Kechadi. Mcrb: A new interconnection network for multiprocessor systems. In Misc. Papers, CD-ROM of the 2002 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'02), ISBN: 1-892512-39-4, Las Vegas, USA, June 2002.
11. M. T. Kechadi and J.-L. Dekeyser. Analysis and simulation of an out-of-order execution model in vector multiprocessor systems. Parallel Computing, 23:1963-1986, 1997.
12. C. Kruskal and M. Snir. A unified theory of interconnection network structure. Theoretical Computer Science, 48:75-94, 1986.
13. C. P. Kruskal and M. Snir. The performance of multistage interconnection networks for mutliprocessors. IEEE Trans. Comput., C-32(12):1091-1098, Dec. 1983.
14. D. A. Lawrie. Access and alignment of data in an array processor. IEEE Trans. Comput., C-24(12):1145-1155, Dec. 1975.
15. J. Lenfant. Parallel permutations of data: A benes network control algorithm for frequently used permutations. IEEE Trans. Comp., C-27:637-647, July 1978.
16. Y.-S. Liu. Architecture and performance of processor-memory interconnection networks for MIMD shared memory parallel processing systems. PhD thesis, New York University, 1990.
17. A. Merchant. Analytical Models for the Performance Analysis of Banyan Networks. PhD thesis, Stanford University, 1991.
18. D. Nassimi and S. Sahni. A self-routing benes network and parallel permutation algorithms. IEEE Trans. Comput., C-30:332-340, May 1981.
19. B. Parhami and D.-M. Kwai. Periodically regular chordal rings. IEEE Transactions on parallel and Distributed Systems, 10(6):658-767, Jun. 1999.
20. J. H. Patel. Performance of processor-memory interconnections for multiprocessors. IEEE. Trans. Comput., C-30(10):771-780, Oct. 1981.
21. I. D. Scherson and A. S. Youssef. Interconnection networks for high-performance parallel computers. IEEE computer society press, 1994.
22. T. Szymanski and V. Harnacher. On the permutation capability of multistage interconnection networks. IEEE Trans. Comp., C-36(7):810-822, Jul. 1987.
23. T. Szymanski and V. Hamacher. On the universality of multistage interconnection networks. In Interconnection Networks for High-Performance Parallel Computers, pages 73-101. IEEE Computer Society Press, 1994.
24. W. Wulf and C. Bell. C.mmp- a multi-mini-processor. In AFIPS Proc. Fall Joint Computer Conf., pages 765-777, 1972. NL.