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Volumn 64, Issue 3, 2004, Pages 345-359

Mapping rectangular mesh algorithms onto asymptotically space-optimal arrays

Author keywords

Allocation function; Dependence graph; Dependence vector; Projection methods; Re indexation; Schedule; Space complexity; System of uniform recurrence equations

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; FUNCTIONS; PARALLEL PROCESSING SYSTEMS; PROBLEM SOLVING; SCHEDULING; VLSI CIRCUITS;

EID: 2942576712     PISSN: 07437315     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.jpdc.2003.04.002     Document Type: Article
Times cited : (4)

References (43)
  • 1
    • 0025495124 scopus 로고
    • Space-time minimal systolic arrays for Gaussian elimination and the algebraic path problem
    • Benaini A., Robert Y. space-time minimal systolic arrays for Gaussian elimination and the algebraic path problem. Parallel Comput. 15:1990;135-158.
    • (1990) Parallel Comput. , vol.15 , pp. 135-158
    • Benaini, A.1    Robert, Y.2
  • 2
    • 0026727329 scopus 로고
    • A processor-time-minimal systolic array for cubical mesh algorithms
    • January
    • Cappello P. A processor-time-minimal systolic array for cubical mesh algorithms. IEEE Trans. Parallel Distrib. Systems. 3(1):January 1992;4-13.
    • (1992) IEEE Trans. Parallel Distrib. Systems , vol.3 , Issue.1 , pp. 4-13
    • Cappello, P.1
  • 3
    • 38249041270 scopus 로고
    • A design methodology for synthesizing parallel algorithms and architectures
    • Chen M.C. A design methodology for synthesizing parallel algorithms and architectures. J. Parallel Distrib. Comput. 3(4):1986;461-491.
    • (1986) J. Parallel Distrib. Comput. , vol.3 , Issue.4 , pp. 461-491
    • Chen, M.C.1
  • 5
    • 0028565287 scopus 로고
    • Optimal mapping of systolic algorithms by regular instructions shifts
    • San Francisco, CA, IEEE Computer Society Press, Silver Spring, MD
    • P. Clauss, G.R. Perrin, Optimal mapping of systolic algorithms by regular instructions shifts, International Conference on Application-Specific Array Processors, ASAP'94, San Francisco, CA, IEEE Computer Society Press, Silver Spring, MD, 1994, pp. 224-235.
    • (1994) International Conference on Application-specific Array Processors, ASAP'94 , pp. 224-235
    • Clauss, P.1    Perrin, G.R.2
  • 8
    • 18744433892 scopus 로고    scopus 로고
    • Derivation of systolic algorithms for the algebraic path problem by recurrence transformations
    • Djamegni C.T., Quinton P., Rajopadhye S., Risset T. Derivation of systolic algorithms for the algebraic path problem by recurrence transformations. Parallel Comput. 26(11):2000;1429-1445.
    • (2000) Parallel Comput. , vol.26 , Issue.11 , pp. 1429-1445
    • Djamegni, C.T.1    Quinton, P.2    Rajopadhye, S.3    Risset, T.4
  • 9
    • 0030092442 scopus 로고    scopus 로고
    • Scheduling of the DAG associated with pipeline inversion of triangular matrices
    • Djamegni C.T., Tchuente M. Scheduling of the DAG associated with pipeline inversion of triangular matrices. Parallel Process. Lett. 6(1):1996;13-26.
    • (1996) Parallel Process. Lett. , vol.6 , Issue.1 , pp. 13-26
    • Djamegni, C.T.1    Tchuente, M.2
  • 10
    • 0034156114 scopus 로고    scopus 로고
    • A new algorithm for dynamic programming on regular arrays
    • Djamegni C.T., Tchuente M. A new algorithm for dynamic programming on regular arrays. Parallel Process. Lett. 10(1):2000;15-27.
    • (2000) Parallel Process. Lett. , vol.10 , Issue.1 , pp. 15-27
    • Djamegni, C.T.1    Tchuente, M.2
  • 11
    • 0030106788 scopus 로고    scopus 로고
    • Optimal synthesis of algorithm-specific lower-dimensional processor arrays
    • March
    • Ganapathy K.N., Wah B.W. Optimal synthesis of algorithm-specific lower-dimensional processor arrays. IEEE Trans. Parallel Distrib. Systems. 7(3):March 1996;274-287.
    • (1996) IEEE Trans. Parallel Distrib. Systems , vol.7 , Issue.3 , pp. 274-287
    • Ganapathy, K.N.1    Wah, B.W.2
  • 12
    • 2942536736 scopus 로고
    • Equivalent transformations on systolic design represented by generating functions
    • Hou Y.C., Tsay J.C. Equivalent transformations on systolic design represented by generating functions. J. Inform. Sci. Eng. 5:1992;229-250.
    • (1992) J. Inform. Sci. Eng. , vol.5 , pp. 229-250
    • Hou, Y.C.1    Tsay, J.C.2
  • 13
    • 0025594842 scopus 로고
    • Design of configurable processor arrays
    • New Orleans
    • M. Huber, J. Teich, L. Thiele, Design of configurable processor arrays, Proceedings of ISCAS'90, New Orleans, 1990, pp. 970-973.
    • (1990) Proceedings of ISCAS'90 , pp. 970-973
    • Huber, M.1    Teich, J.2    Thiele, L.3
  • 14
    • 0001512318 scopus 로고
    • The organization of computations for uniform recurrence equations
    • Karp R.M., Miller R.E., Winograd S. The organization of computations for uniform recurrence equations. J. ACM. 14(3):1967;563-590.
    • (1967) J. ACM , vol.14 , Issue.3 , pp. 563-590
    • Karp, R.M.1    Miller, R.E.2    Winograd, S.3
  • 15
    • 0002842254 scopus 로고
    • Systolic arrays (for VLSI)
    • I.S. Duff, et al. (Eds.), Sparse Matrix
    • H.T. Kung, C.E. Leiserson, Systolic arrays (for VLSI), in: I.S. Duff, et al. (Eds.), Sparse Matrix, Proc. Soc. Ind. App. Math., 1979, pp. 256-282.
    • (1979) Proc. Soc. Ind. App. Math. , pp. 256-282
    • Kung, H.T.1    Leiserson, C.E.2
  • 16
    • 0016026944 scopus 로고
    • The parallel execution of do loops
    • Lamport L. The parallel execution of Do loops. Commun. ACM. 17(2):1974;83-93.
    • (1974) Commun. ACM , vol.17 , Issue.2 , pp. 83-93
    • Lamport, L.1
  • 17
    • 2942568579 scopus 로고    scopus 로고
    • Solutions to the communication minimization problem for affine recurrence equations
    • February
    • V. Loechner, C. Mongenet, Solutions to the communication minimization problem for affine recurrence equations, ICPS RR 97-06, February 1997, http://icps.u-strasbg.fr/pub-97/.
    • (1997) ICPS RR , vol.97 , Issue.6
    • Loechner, V.1    Mongenet, C.2
  • 19
    • 0021473589 scopus 로고
    • A mathematical model for the verification of systolic networks
    • Melhem R.G., Rheinboldt W.C. A mathematical model for the verification of systolic networks. SIAM J. Comput. 13:1984;541-565.
    • (1984) SIAM J. Comput. , vol.13 , pp. 541-565
    • Melhem, R.G.1    Rheinboldt, W.C.2
  • 20
    • 0024716237 scopus 로고
    • Minimum distance: A method for partitioning recurrences for multiprocessors
    • August
    • Peir J.K., Cytron R. Minimum distance: a method for partitioning recurrences for multiprocessors. IEEE Trans. Comput. 38(8):August 1989;1203-1211.
    • (1989) IEEE Trans. Comput. , vol.38 , Issue.8 , pp. 1203-1211
    • Peir, J.K.1    Cytron, R.2
  • 22
    • 51249173427 scopus 로고
    • The mapping of linear equations on regular arrays
    • Quinton P., Dongen V.V. The mapping of linear equations on regular arrays. J. VLSI Signal Process. 1(2):1989;95-113.
    • (1989) J. VLSI Signal Process. , vol.1 , Issue.2 , pp. 95-113
    • Quinton, P.1    Dongen, V.V.2
  • 23
    • 0024663338 scopus 로고
    • Synthesizing systolic arrays with control signal from recurrence equations
    • Rajopadhye S.V. Synthesizing systolic arrays with control signal from recurrence equations. Distrib. Comput. 3:1989;88-105.
    • (1989) Distrib. Comput. , vol.3 , pp. 88-105
    • Rajopadhye, S.V.1
  • 24
    • 0025446495 scopus 로고
    • Synthesizing systolic arrays from recurrences equations
    • Rajopadhye S.V., Fujimoto R.M. Synthesizing systolic arrays from recurrences equations. Parallel Comput. 14:1990;163-189.
    • (1990) Parallel Comput. , vol.14 , pp. 163-189
    • Rajopadhye, S.V.1    Fujimoto, R.M.2
  • 26
    • 0023984385 scopus 로고
    • Regular iterative algorithms and their implementation on processors arrays
    • Rao S., Kailath T. Regular iterative algorithms and their implementation on processors arrays. Proc. IEEE. 76(4):1988;259-269.
    • (1988) Proc. IEEE , vol.76 , Issue.4 , pp. 259-269
    • Rao, S.1    Kailath, T.2
  • 27
    • 2942594658 scopus 로고
    • Méthode de conception d'algorithmes paralleles pour réseaux reguliers
    • Sakho I., Tchuente M. Méthode de conception d'algorithmes paralleles pour réseaux reguliers. Tech. Sci. Inform. 8:1989;63-72.
    • (1989) Tech. Sci. Inform. , vol.8 , pp. 63-72
    • Sakho, I.1    Tchuente, M.2
  • 29
    • 2942539320 scopus 로고    scopus 로고
    • A processor-time minimal design for 3D rectilinear mesh algorithms
    • Scheiman C., Cappello P. A processor-time minimal design for 3D rectilinear mesh algorithms. Parallel Process. Lett. 6(4):1996;539-550.
    • (1996) Parallel Process. Lett. , vol.6 , Issue.4 , pp. 539-550
    • Scheiman, C.1    Cappello, P.2
  • 30
    • 0026171591 scopus 로고
    • Time optimal linear schedules for algorithms with uniform dependencies
    • Shang W., Fortes J.A.B. Time optimal linear schedules for algorithms with uniform dependencies. IEEE Trans. Comput. 40:1991;723-742.
    • (1991) IEEE Trans. Comput. , vol.40 , pp. 723-742
    • Shang, W.1    Fortes, J.A.B.2
  • 31
    • 0002140529 scopus 로고
    • On mapping of uniform dependence algorithms into lower dimensional processors arrays
    • Shang W., Fortes J.A.B. On mapping of uniform dependence algorithms into lower dimensional processors arrays. IEEE Trans. Parallel Distrib. Systems. 3:1992;350-363.
    • (1992) IEEE Trans. Parallel Distrib. Systems , vol.3 , pp. 350-363
    • Shang, W.1    Fortes, J.A.B.2
  • 32
    • 0026227272 scopus 로고
    • Synthesis of ASIC regular arrays for real-time image processing systems
    • Swaaij M.V., Rosseel J., Catthoor F., Man H.D. Synthesis of ASIC regular arrays for real-time image processing systems. J. VLSI Signal Process. 3:1991;183-192.
    • (1991) J. VLSI Signal Process. , vol.3 , pp. 183-192
    • Swaaij, M.V.1    Rosseel, J.2    Catthoor, F.3    Man, H.D.4
  • 34
    • 0026171253 scopus 로고
    • Control generation in the design of processor arrays
    • Teich J., Thiele L. Control generation in the design of processor arrays. J. VLSI Signal Process. 3:1991;77-92.
    • (1991) J. VLSI Signal Process. , vol.3 , pp. 77-92
    • Teich, J.1    Thiele, L.2
  • 35
    • 0027541568 scopus 로고
    • Partitioning of processor arrays: A piecewise regular approach
    • Teich J., Thiele L. Partitioning of processor arrays: a piecewise regular approach. INTEGRATION, VLSI J. 14:1993;297-332.
    • (1993) Integration, VLSI J. , vol.14 , pp. 297-332
    • Teich, J.1    Thiele, L.2
  • 36
    • 0029349837 scopus 로고
    • Resource constrained scheduling of uniform algorithms
    • August
    • Thiele L. Resource constrained scheduling of uniform algorithms. J. VLSI Signal Process. 10(3):August 1995;295-310.
    • (1995) J. VLSI Signal Process. , vol.10 , Issue.3 , pp. 295-310
    • Thiele, L.1
  • 37
    • 2942566509 scopus 로고
    • Systematic design of local processor arrays for numerical algorithms
    • E.F. Deprettere, A.J. Van der Veen (Eds.), Elsevier, Amsterdam
    • L. Thiele, V. Roychowdhury, Systematic design of local processor arrays for numerical algorithms, in: E.F. Deprettere, A.J. Van der Veen (Eds.), Algorithms and Parallel VLSI Architectures, Vol. A: Tutorials, Elsevier, Amsterdam, 1991, pp. 329-339.
    • (1991) Algorithms and Parallel VLSI Architectures, Vol. A: Tutorials , vol.A , pp. 329-339
    • Thiele, L.1    Roychowdhury, V.2
  • 38
    • 0029307680 scopus 로고
    • Design of space-optimal regular arrays for algorithms with linear schedules
    • Tsay J.C., Chang P.Y. Design of space-optimal regular arrays for algorithms with linear schedules. IEEE Trans. Comput. 44(5):1995;683-694.
    • (1995) IEEE Trans. Comput. , vol.44 , Issue.5 , pp. 683-694
    • Tsay, J.C.1    Chang, P.Y.2
  • 39
    • 0001920445 scopus 로고
    • Quasi-regular arrays: Definition and design methodology
    • J. McCanny, J. McWhirter, E. Swartzlander (Eds.). Killarney, Co. Kerry, Ireland, Prentice-Hall, Englewood Cliffs, NJ
    • V. Van Dongen, Quasi-regular arrays: definition and design methodology, in: J. McCanny, J. McWhirter, E. Swartzlander (Eds.), Systolic Array Processors. Proc. Int. Conf. on Systolic Arrays. Killarney, Co. Kerry, Ireland, Prentice-Hall, Englewood Cliffs, NJ, 1989, pp. 126-135.
    • (1989) Systolic Array Processors. Proc. Int. Conf. on Systolic Arrays , pp. 126-135
    • Van Dongen, V.1
  • 41
    • 0026821873 scopus 로고
    • Transformation of broadcasts into propagations in systolic algorithms
    • Wong Y., Delosme J.M. Transformation of broadcasts into propagations in systolic algorithms. J. Parallel Distrib. Comput. 14:1992;121-145.
    • (1992) J. Parallel Distrib. Comput. , vol.14 , pp. 121-145
    • Wong, Y.1    Delosme, J.M.2
  • 42
    • 2942566673 scopus 로고
    • Specifying control signals for systolic arrays by uniform recurrence equations
    • Xue J. Specifying control signals for systolic arrays by uniform recurrence equations. Parallel Process. Lett. 1:1991;83-93.
    • (1991) Parallel Process. Lett. , vol.1 , pp. 83-93
    • Xue, J.1
  • 43
    • 0006481077 scopus 로고
    • The formal synthesis of control signals for systolic arrays
    • Ph.D. Thesis, Department of Computer Science, University of Edinburgh
    • J. Xue, The formal synthesis of control signals for systolic arrays, Ph.D. Thesis, Technical Report ECS-LFCS-92-203, Department of Computer Science, University of Edinburgh, 1992.
    • (1992) Technical Report , vol.ECS-LFCS-92-203
    • Xue, J.1


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