Package parasitics influence efficiency

Power Electronics Technology

Volumn 31, Issue 11, 2005, Pages

  Lee, John ^a  

^a Vishay   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PAK SO-8 PACKAGES; PARASITIC INDUCTION; STANDARD SO-8 PACKAGE; SWITCHING TIME;

ELECTRIC CONVERTERS; ELECTRIC LOSSES; HEAT CONDUCTION; SWITCHING;

ELECTRONICS PACKAGING;

EID: 29344433046     PISSN: 15402800     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Review

References (5)

1. Pavier, Mark, et al. "High Frequency DC-DC Power Conversion: The Influence of Package Parasitics," IEEE APEC 2003.
2. Xiao, Y., et al. "Analytical Modeling and Experimental Evaluation of Interconnect Parasitic Inductance on MOSFET Switching Characteristics," IEEE APEC 2004.
3. Cronje, W.A.; Van Wyk, J.D.; and Van Wyk, J.D., Jr. "A Systematic Approach to Modeling of Layout Parasitics in Converter-Initial Formulation," Proc. of IEEE Power Electronics Specialist Conference 1998, pp. 1944-1950, 1998.
4. Ejury, J., and Elbanhawy, A. "Investigations of the Influence of PCB Layout Parasitic Inductances in DC-DC Converters on the Efficiency," International PCIM Europe Conference 2004, pp. 31-36.
5. Nobauer, G., Ahlers, D., and Sevillano-Ruiz, J. "A Method to Determine Parasitic Inductances in Buck Converter Topologies," International PCIM Europe Conference 2004, PP. 37-41.