Hardware implementation analysis of SHA-256 and SHA-512 algorithms on FPGAs

Computers and Electrical Engineering

Volumn 31, Issue 6, 2005, Pages 345-360

  Ahmad, Imtiaz ^a   Das, A Shoba ^a  

^a KUWAIT UNIVERSITY   (Kuwait)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKING FREQUENCY; HASH FUNCTIONS; HASH VALUE;

ALGORITHMS; COMPUTATION THEORY; FIELD PROGRAMMABLE GATE ARRAYS;

COMPUTER HARDWARE;

EID: 29144532671     PISSN: 00457906     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.compeleceng.2005.07.001     Document Type: Article

References (21)

1. C. Kaufman, R. Perlman, and M. Speciner Network security: private communication in a public world 2nd ed. 2002 Prentice-Hall
2. FIPS Publication 198. The Keyed-hash message authentication code (HMAC). US Doc/NIST, March 6, 2002.
3. Madson C, Glenn R. The use of HMAC-SHA-1-96 within ESP and AH. RFC 2404, November 1998.
4. Rivest RL. The MD5 message digest algorithm. RFC 1321, April 1992.
5. FIPS Publication 180-1. Secure hash standard (SHS). US Doc/NIST, April 17, 1995.
6. FIPS Publication 197. Advanced encryption standard (AES). US Doc/NIST, November 26, 2001.
7. FIPS Publication 180-2. Secure hash standard (SHS). US Doc/NIST, May 30, 2001.
8. FIPS Publication 180-2. Secure hash standard (SHS) change notice 1. US Doc/NIST, February 2004.
9. A. Booselaers, R. Govaerts, and J. Vandewalle Fast hashing on Pentium Proceedings of Crypto'96, LNCS 1109 1996 Springer-Verlag 298 312
10. A. Booselaers, R. Govaerts, and J. Vandewalle SHA: a design for parallel architectures? Proceedings of the EUROCRYPT'97, LNCS 1233 1997 Springer-Verlag 348 362
11. J. Nakajima, and M. Matsui Performance analysis and parallel implementation of dedicated hash functions on Pentium III IEICE Transactions on Fundamentals E86-A 1 2003 54 63
12. Dominikus S. A hardware implementation of MD5-family hash algorithm. In: Proceedings of the international conference on electronics circuits and systems, Dubrovnik, Croatia, September 15-18, 2002. p. 1143-6.
13. McLoone M, McCanny JV. Efficient single-chip implementation of SHA-384 and SHA-512. In: Proceedings of the IEEE international conference on field-programmable technology (FPT), Hong Kong, July 2002. p. 311-4.
14. Kang YK, Kim DW, Kwon TW, Choi JR. An efficient implementation of hash function processor for IPSEC. In: Proceedings of the Asia-Pacific conference on ASICs, August 2002. p. 93-6.
15. T. Grembowski, R. Lien, K. Gaj, N. Nguyen, P. Bellows, and J. Flidr Comparative analysis of the hardware implementation of hash functions SHA-1 and SHA-512 Proceedings of the 5th international conference on information security (ISC'2002), LNCS 2433 2002 Springer-Verlag 75 89
16. Sklavos N, Koufopavlou O. On the hardware implementation of the SHA-2 (256, 384, 512) hash functions. In: Proceedings of the IEEE international symposium on circuits and systems, vol. 5, May 2003. p. 153-6.
17. Dadda L, Macchetti M. The design of a high speed ASIC unit for the hash functions SHA-256 (384, 512). In: Proceedings of the design, automation and test in Europe conference (DATE'04), February 16-20, 2004.
18. M.D. Ercegovac, and T. Lang Digital arithmetic 2004 Morgan Kaufmann Publishers
19. Kaliski B, Staddon J. RSA cryptography specifications-Version 2.0. RFC 2437, October 1998.
20. Haller N, Metz C, Nesser P, Straw M. A one-time password system. RFC 2289, February 1998.
21. Dierks T, Allen C. The TLS protocol-Version 1.0. RFC 2246, January 1999.