FPGA implementation of a delay-line readout system for a particle detector

Measurement: Journal of the International Measurement Confederation

Volumn 39, Issue 1, 2006, Pages 90-99

  Seferiadis, G ^a   Pouchet, M ^a   Gough, M P ^a  

^a UNIVERSITY OF SUSSEX   (United Kingdom)

Author keywords

Delay line; FPGA; Oscillator

Indexed keywords

COMPUTER SIMULATION; COSTS; ELECTRIC DELAY LINES; MICROPROCESSOR CHIPS; OSCILLATORS (ELECTRONIC); PARTICLE DETECTORS; READOUT SYSTEMS;

DELAY CHAINS; DELAY ELEMENTS; FPGA IMPLEMENTATION; TIME TO DIGITAL CONVERSION (TDC);

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 28844506603     PISSN: 02632241     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.measurement.2005.07.003     Document Type: Article

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