Design for manufacturing strategies to bring silicon process to 32nm node

IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings

Volumn , Issue , 2005, Pages 101-104

  Chen, J Fung ^a   Staud, Wolf ^b   Arnold, Bill ^a  

^a ASML US Inc   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONSTRAINT THEORY; INTEGRATED CIRCUIT LAYOUT; LITHOGRAPHY; OPTIMIZATION; PRODUCT DESIGN; SILICON;

PROCESS MODEL FILE (PMF); RESOLUTION ENHANCEMENT TECHNOLOGY (RET);

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 28744452518     PISSN: 1523553X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/issm.2005.1513307     Document Type: Conference Paper

References (2)

1. J. Fung Chen et al, "RET Masks for the Final Frontier of Optical Lithography," SPIE Vol. 5853, pp 168-179, April 2005.
2. Cadence and ASML MaskTools jointly developed the concept of PMF and the use models. The credit goes to all of the joint development team members.