A novel approach for the patterning and high-volume production of Sub-40-nm gates

IEEE Transactions on Semiconductor Manufacturing

Volumn 18, Issue 4, 2005, Pages 539-544

  Romero, Karla ^a,d   Stephan, Rolf ^a   Grasshoff, Gunter ^a,e   Mazur, Martin ^a,b,f   Ruelke, Hartmut ^a,g,h   Huy, Katja ^b,i   Klais, Jochen ^b,c,j   McGowan, Sarah ^c,h   Dakshina Murthy, Srikanteswara ^c,h   Bell, Scott ^c,k   Wright, Marilyn ^c,l  

^a Etch Module   (Germany)

^b IBM MICROELECTRONICS   (United States)

^c ADVANCED MICRO DEVICES   (United States)

^d Gate Integration for Advanced Micro Devices (AMD) 300 mm Fab36   (Germany)

^e FEOL Etch Process Engineering Group

^f FEOL Process Development

^g Advanced Micro Devices (AMD) 300 mm Facility   (Germany)

^h Defect Yield Enhancement Group in Fab30 ^*  (Singapore)

ⁱ Thin Films Group FAB30

^j Defect Yield Enhancement Group in Fab30

^k Advanced Process Development Group   (United States)

^l Logic Technology Development   (United States)

more..

Author keywords

Amorphous carbon; Etching; Extendibility; Gate patterning; Hardmask

Indexed keywords

AMORPHOUS CARBON; GATE PATTERNING; HARDMASK; PATTERNING LAYER;

AMORPHOUS MATERIALS; CARBON; ETCHING;

GATES (TRANSISTOR);

EID: 28644436193     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2005.858518     Document Type: Conference Paper

References (7)

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