Poly-Si gate patterning issues for ultimate MOSFET

Microelectronic Engineering

Volumn 61, Issue 62, 2002, Pages 859-865

  Louis, D ^a   Nier, M E ^a,b   Fery, C ^a   Heitzmann, M ^a   Papon, A M ^a   Renard, S ^a,b  

^a CEA GRENOBLE   (France)

^b STMICROELECTRONICS   (France)

Author keywords

Critical dimension; Etching; Gate; Hard mask; Notch

Indexed keywords

ELECTRON BEAM LITHOGRAPHY; ETCHING; GATES (TRANSISTOR); MASKS; PHOTORESISTS; PHOTOSENSITIVITY; POLYSILICON;

CRITICAL DIMENSIONS (CD);

MOSFET DEVICES;

EID: 0036643656     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(02)00437-9     Document Type: Article

References (7)

1. Process development for 30 nm poly gate patterning on 1.2 nm oxide
2. Fabrication of single electron devices by hybrid (E-beam/DUV) lithography
3. A 20 nm physical gate length NMOS FET featuring 1.2 nm gate oxide, shallow implanted source and drain and BF2 pockets