Energy-efficient design

IEEE Micro

Volumn 25, Issue 5, 2005, Pages 6-9

  Uchiyama, Kunio ^a   Bose, Prapid ^b   Hofstee, H Peter ^b  

^a Hitachi ^*  (Japan)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28244483793     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2005.89     Document Type: Editorial

References (3)

1. K. Kutaragi et al., "A Micro Processor with a 128b CPU, 10 Floating-Point MACs, Floating-Point Dividers, and an MPEG2 Decoder," Int'l Solid-State Circuits Conf. Digest of Technical Papers (ISSCC 99), IEEE Press, 1999, pp. 256-257.
2. A. Kunimatsu et al., "Vector Unit Architecture for Emotion Synthesis," IEEE Micro, vol. 20, no. 2, Mar.-Apr. 2000, pp. 40-47.
3. J.H. Kahle et al., "Introduction to Cell," IBM J. Research and Development, vol. 49, no. 4/5, July-Sep. 2005, pp. 589-604.