The impact of technology on power for high-speed electrical and optical interconnects

Proceedings of the IEEE 2005 International Interconnect Technology Conference, IITC

Volumn , Issue , 2005, Pages 177-179

  Cho, Hoyeol ^a   Kapur, Pawan ^a   Saraswat, Krishna C ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BIT ERROR RATE; CAPACITANCE; ENERGY DISSIPATION; PERFORMANCE; TRANSISTORS;

INTER-CHIP COMMUNICATION; POWER DISSIPATION; TECHNOLOGY SCALING; TRANSISTOR PERFORMANCE;

OPTICAL INTERCONNECTS;

EID: 28244475712     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. International Technology Roadmap for Semiconductor (ITRS), 2003, San Jose, CA: Semiconductor Industry Association.
2. Cho et. al., Int. Inter. Techn. Conf. (IITC), pp. 116-18, 2004.
3. Cho et. al., J. Lightwave Tech. vol.22, pp. 2021-33, Sept. 2004.
4. Kibar et. al., J. Lightwave Tech., vol.17, pp.546-55, Apr. 1999.
5. Kapur et. al., Int. Inter. Techn. Conf. (IITC), pp.89-91, 2002.
6. Bhatanger et. al., J. Lightwave Tech., vol22, pp.2223-2227, Sept. 2004