45nm-node BEOL integration featuring porous-ultra-low-K/Cu multilevel interconnects

Proceedings of the IEEE 2005 International Interconnect Technology Conference, IITC

Volumn , Issue , 2005, Pages 15-17

  Sugiura, I ^a   Nakata, Y ^a   Misawa, N ^a   Otsuka, S ^a   Nishikawa, N ^a   Iba, Y ^a   Sugimoto, F ^a   Setta, Y ^a   Sakai, H ^a   Mizushima, Y ^a   Kotaka, Y ^a   Uchibori, C ^a   Suzuki, T ^a   Kitada, H ^a   Koura, Y ^a   Nakano, K ^a   Karasawa, T ^a   Ohkura, Y ^a   Watatani, H ^a   Sato, M ^a   Nakai, S ^a   Nakaishi, M ^a   Shimizu, N ^a   Fukuyama, S ^a   Miyajima, M ^a   Nakamura, T ^a   Yano, E ^a   Watanabe, K ^a   more..

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC PROPERTIES; ELECTRIC FIELDS; OPTIMIZATION; POROUS MATERIALS; SILICA; SILICON WAFERS;

APPLIED VOLTAGE; INSULATING PROPERTY; ULTRA-LOW-K MATERIALS;

LARGE SCALE SYSTEMS;

EID: 28244455277     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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3. M. Ikeda et al., Proc. IITC, 71 (2003).
4. M. Shimada et al., Proc. IITC, 178 (2004).
5. T. Suzuki et al., Jpn. J. Appl. Phys., 43, L614 (2004).
6. E. Morifuji et al., VLSI Symp. Tech. Dig., 164 (2004).