High-tension power delivery: Operating 0.18μm CMOS digital logic at 5.4V

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Rajapandian, Saravanan ^a   Shepard, Kenneth ^a   Hazucha, Peter ^b   Karnik, Tanay ^b  

^a Och Spine at New York Presbyterian Hospitals   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144459387     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. G.-Y. Wei and M. Horowitz, "A Fully Digital, Energy-Efficient Adaptive Power-Supply Regulator," IEEE J. Solid-State Circuits, vol. 35, pp. 520-528, April, 2000.
2. S. Rajapandian and K. L. Shepard, "Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits Through Charge-Recycling," Symp. VLSI Circuits, pp. 330-333, June, 2004.
3. P. Hazucha et al., "An Area-Efficient, Integrated, Linear Regulator with Ultra-Fast Load Regulation," Symp. VLSI Circuits, pp. 218-221, June, 2004.