Two-resistor compact modeling for multiple die and multi-chip packages

Annual IEEE Semiconductor Thermal Measurement and Management Symposium

Volumn , Issue , 2005, Pages 327-334

  Garcia, Enrico A ^a   Chiu, Chia Pin ^b  

^a Intel Technology Philippines Inc   (Philippines)

^b INTEL CORPORATION   (United States)

Author keywords

Chip scale; Compact; Stacked; Two resistor

Indexed keywords

CHIP-SCALE; COMPACT; STACKED; TWO-RESISTORS;

BOUNDARY CONDITIONS; CHIP SCALE PACKAGES; DIES; HEAT RESISTANCE; MICROPROCESSOR CHIPS; PLATES (STRUCTURAL COMPONENTS);

RESISTORS;

EID: 28144458343     PISSN: 10652221     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/STHERM.2005.1412200     Document Type: Conference Paper

References (7)

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3. Young Gon Kim, "Folded Stack Package Development," Proceedings of 52nd Electronic Components and Technology Conference, San Diego, California, 2002.
4. David W. Stiver and Sarang Shidore, "The extraction of a Two-Resistor/Two-Capacitor Model for Common IC Packages and their Implementation in CFD," Proceedings of IMAPS 2002, Denver, Colorado, 2002.
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6. JEDEC Standard: JESD 51-8, "Integrated Circuit Thermal Test Method Environmental Conditions - Junction-to-Board," October 1999.
7. EIA/JEDEC Standard: JESD 51-9, "Test Boards for Area Array Surface Mount Package Thermal Measurements," July 2000.