A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty

Materials Research Society Symposium - Proceedings

Volumn 626, Issue , 2001, Pages

  Velenis, D ^a   Friedman, E G ^a   Papaefthymiou, M C ^a  

^a University of Rochester   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CLOCKS; DELAY CIRCUITS; UNCERTAIN SYSTEMS;

CLOCK DISTRIBUTION NETWORKS; CLOCK SIGNALS; HIGH SPEED SYNCHRONOUS CIRCUITS;

MICROELECTRONICS;

EID: 0035026718     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)