Optimizing the IC delamination quality via six-sigma approach

IEEE Transactions on Electronics Packaging Manufacturing

Volumn 28, Issue 3, 2005, Pages 241-248

  Su, Chao Ton ^a   Chiang, Tai Lin ^b   Chiao, Kevin ^c  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b MINGHSIN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Taiwan)

^c MACRONIX INTERNATIONAL CO LTD   (Taiwan)

Author keywords

Delamination; Integrated circuits (IC); Machine to machine study (MTM); Six sigma; Surface mount technology (SMT)

Indexed keywords

CHIP SCALE PACKAGES; DELAMINATION; INTEGRATED CIRCUIT MANUFACTURE; OPTIMIZATION; RELIABILITY THEORY;

MACHINE-TO-MACHINE STUDY (MTM); RELIABILITY TESTING; SIX SIGMA APPROACH;

SURFACE MOUNT TECHNOLOGY;

EID: 27844447133     PISSN: 1521334X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEPM.2005.852233     Document Type: Article

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