Conflict analysis in multiprocess synthesis for optimized system integration

CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis

Volumn , Issue , 2005, Pages 15-20

  Bringmann, Oliver ^a   Siebenborn, Axel ^a   Rosenstiel, Wolfgang ^b  

^a FZI RESEARCH CENTER FOR INFORMATION TECHNOLOGY   (Germany)

^b UNIVERSITY OF TÜBINGEN   (Germany)

Author keywords

Behavioral Synthesis; Binding; Concurrent Systems; Scheduling; System Level Design; Systems on Chip

Indexed keywords

OPTIMIZATION; RESOURCE ALLOCATION; SCHEDULING; STORAGE ALLOCATION (COMPUTER);

BEHAVIORAL SYNTHESIS; CONCURRENT SYSTEMS; SYSTEM LEVEL DESIGN;

MULTIPROCESSING PROGRAMS;

EID: 27644450042     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1084834.1084844     Document Type: Conference Paper

References (17)

1. J. K. Adams, D. E. Thomas: Multiple-Process Behavioral Synthesis for Mixed Hardware-Software Systems, Proceedings of Internatinal Symposium on System Synthesis (ISSS), 1995.
2. K. Bilinski, J. Mirkowski, E. L. Dagless: Synchronous Parallel Controller Synthesis from Behavioural Multiple-process VHDL Description; Proceedings of EURO-DAC/EURO-VHDL, 1996.
3. O. Bringmann, W. Rosenstiel, D. Reichardt: Synchronization Detection for Multi-Process Hierarchical Synthesis; Proceedings of international Symposium on System Synthesis (ISSS), 1998.
4. O. Bringmann, W. Rosenstiel: Resource Sharing in Hierarchical Synthesis; Intl. Conf. on Computer Aided Design (ICCAD), 1997.
5. J.-M. Chang, M. Pedram: Codex-dp: Co-Design of Communicating Systems Using Dynamic Programming; IEEE Transactions on Computer-Aided Design, Vol. 19. No. 7, 2000.
6. C. N. Coelho, Jr., G. De Micheli: Analysis and Synthesis of Concurrent Digital Circuits Using Control-Flow Expressions; IEEE Transactions on Computer-Aided Design, Vol. 15, No. 8, 1996.
7. P. Eles, K. Kuchcinski, Z. Peng: Synthesis of Systems Specified as Interacting VHDL Processes; Integration the VLSI Journal, Vol. 21, pp. 113-138, 1996.
8. J. W. Hagennan: Synthesis of Multiple Process Digital Systems; PhD Thesis, Carnegie Mellon University, 1994.
9. [91 C. Jäschkc, F. Beckmann, R. Laur: Time Constrained Modulo Scheduling with Global Resource Sharing; Proceedings of Design, Automation and Test in Europe (DATE), 1999.
10. C. Jäschke, R. Laur: Resource Constrained Modulo Scheduling with Global Resource Sharing; Proceeding of International Symposium on System Synthesis (ISSS), 1998.
11. P. G. Paulin, J. P. Knight: Force-Directed Scheduling for the Behavioral Synthesis of ASICs; IEEE Transactions on Computer-Aided Design, Vol. 8, Nr. 6, 1989.
12. W. Pugh: The Omega Test: a fast and practical integer programming algorithm for dependence analysis. Proc. of Supercomputing, 1991.
13. S. Sarkar, A. Basu, A.K. Majurndar; Synchronization of Communicating Modules and Processes in High-Level Synthesis; Proceedings of International Conference on VLSI Design, 1995.
14. A. Siebenborn, O. Bringmann, and W. Rosenstiei. Communication Analysis for System-on-Chip Design; Proceedings of DATE, 2004.
15. A. Siebenborn, O. Bringmann, and W. Rosenstiei. Worst-Case Performance Analysis of Parallel, Communicating Software Processes; Proceedings of CODES, 2002.
16. W. Wang, A. Raghunathan, N. K. Jha, S. Dey: Resource Budgeting for Multiprocess High-Level Synthesis; IEEE Transactions on Computer-Aided Design, Vol. 23, No. 7, 2004.
17. W. Wolf, R. Manno: High-Level Modelling and Synthesis of Communicating Processes Using VHDL; IEICE Transactions on Information and Systems, Vol. E76-D, No. 9, 1995.