A 0.168μm 2/0.11μm 2 highly scalable high performance embedded DRAM cell for 90/65-nm logic applications

2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers

Volumn , Issue , 2005, Pages 31-32

  Wang, G ^a   Parries, P ^a   Khan, B ^a   Liu, J ^a   Otani, Y ^a   Norum, J ^a   Robson, N ^a   Kirihata, T ^a   Iyer, S S ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELL SIZE; DRAM CELLS; TRENCH CAPACITORS;

CAPACITORS; ELECTRIC POTENTIAL; EMBEDDED SYSTEMS; TRANSISTORS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 27144528242     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2005.1497070     Document Type: Conference Paper

References (4)

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3. J. Beintner et al, VLSI-TSA Symp., pp. 243-6, Oct. 2003.
4. T. Kirihata et al, ISSCC Dig. Tech. Papers, pp. 206-7, Feb. 2004.