Hardware architecture for genetic algorithms

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3533 LNAI, Issue , 2005, Pages 554-556

  Nedjah, Nadia ^a   De Macedo Mourelle, Luiza ^a  

^a STATE UNIVERSITY OF RIO DE JANEIRO   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; COMPUTATIONAL METHODS; COMPUTER HARDWARE; GENETIC ALGORITHMS; NEURAL NETWORKS;

FITNESS COMPUTATION; HARDWARE ARCHITECTURE;

COMPUTER ARCHITECTURE;

EID: 26944482721     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11504894_76     Document Type: Conference Paper

References (5)

1. Bland, I. M. and Megson, G. M., Implementing a generic systolic array for genetic algorithms. In Proc. 1st. On-Line Workshop on Soft Computing, pp 268-273, 1996.
2. Liu, J., A general purpose hardware implementation of genetic algorithms, MSc. Thesis, University of North Carolina, 1993.
3. Nedjah, N. and Mourelle, L.M., Reconfigurable Hardware Architecture for Compact and Efficient Stochastic Neuron, Artificial Neural Nets Problem Solving Methods, Lecture Notes in Computer Science, vol. 2687, pp. 17-24, 2003.
4. Scott, S.D., Samal, A. and Seth, S., HGA: a hardware-based genetic algorithm, In Proc. ACM/SIGDA 3rd. International Symposium in Field-Programmable Gate Array, pp. 53-59, 1995.
5. Turton, B.H. and Arslan, T., A parallel genetic VLSI architecture for combinatorial real-time applications - disc scheduling, In Proc. IEE/IEEE International Conference on genetic Algorithms in Engineering Systems, pp.88-93, 1994.