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Volumn 19, Issue 12, 2000, Pages 1428-1447

An industrial view of electronic design automation

Author keywords

Emulation; Formal verification; High level synthesis; Logic synthesis; Physical synthesis; Placement; Routing; RTL synthesis; Simulation; Simulation acceleration; Testing; Verification

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; DESIGN FOR TESTABILITY; FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0034428916     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.898825     Document Type: Article
Times cited : (65)

References (121)
  • 5
    • 0029354779 scopus 로고    scopus 로고
    • (1995) Recent developments in netlist partitioning: A survey. [Online], vol (1-2), pp. 1-81. Available: http://vlsicad.cs.ucla.edu/ cheese/survey.html
    • C. J. Alpert and A. B. Kahng. (1995) Recent developments in netlist partitioning: A survey. Integration: VLSIJ. [Online], vol (1-2), pp. 1-81. Available: http://vlsicad.cs.ucla.edu/ cheese/survey.html
    • Integration: VLSIJ
    • Alpert, C.J.1    Kahng, A.B.2
  • 29
    • 33747491920 scopus 로고    scopus 로고
    • Sept. 1999.
    • D. Chapiro, "Verification myths-Automating verification using testbench languages," Electron. Eng., Sept. 1999.
  • 37
    • 34047158089 scopus 로고    scopus 로고
    • Application Specific Programmable Products: The Coming Revolution in System Integration: ASIC-WW-PP9811.
    • Dataquest, , San Jose, CA, Application Specific Programmable Products: The Coming Revolution in System Integration: ASIC-WW-PP9811.
    • , San Jose, CA
    • Dataquest1
  • 111
    • 33747495863 scopus 로고    scopus 로고
    • CA. [Online]. Available: http://www.synopsys.com/products/staticverif/staticver_wp.html
    • (1998) Multimillion-gate ASIC verification. Synopsys, Inc., Mountain View, CA. [Online]. Available: http://www.synopsys.com/products/staticverif/staticver_wp.html
  • 112
    • 33747489533 scopus 로고    scopus 로고
    • CA. [Online]. Available: http://www.synopsys.com/products/verification/formality_bgr.html
    • (1998) Formal verification equivalence checker methodology backgrounder. Synopsys, Inc., Mountain View, CA. [Online]. Available: http://www.synopsys.com/products/verification/formality_bgr.html
  • 113
    • 33747477438 scopus 로고    scopus 로고
    • CA. [Online]. Available: http://www.synopsys.com/products/hwsw/practical_guide.html
    • (1999) Balancing your design cycle, a practical guide to HW/SW co-verification. Synopsys, Inc., Mountain View, CA. [Online]. Available: http://www.synopsys.com/products/hwsw/practical_guide.html


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.