SCOPUS 정보 검색 플랫폼

Volumn 3553, Issue , 2005, Pages 334-343

A scalable embedded JPEG2000 architecture

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE COMPRESSION; RAPID PROTOTYPING; STANDARDS;

JPEG2000 ENCODER; SCALABILITY; TIME-TO-MARKET WINDOW;

EMBEDDED SYSTEMS;

EID: 26444502003 PISSN: 03029743 EISSN: None Source Type: Conference Proceeding
DOI: 10.1007/11512622_36 Document Type: Conference Paper

Times cited : (6)

References (12)

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- ISO/IEC International Standard 15444-1. ITU Recommendation T.800
- JPEG2000 image coding system, ISO/IEC International Standard 15444-1. ITU Recommendation T.800 (2000)
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2
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- Cast Inc.
- JPEG2000 Encoder Core. Cast Inc. (2002)
- (2002) JPEG2000 Encoder Core

3
- 26444451801
- Amphion
- CS6510 JPEG2000 Encoder. Amphion (http://www.amphion.com/cs6510.html)
- CS6510 JPEG2000 Encoder

4
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- A high-performance JPEG2000 architecture
- Andra, K., Chakrabarti, C., Acharya, T.: A high-performance JPEG2000 architecture. IEEE CSVT 13 (2003) 209-218
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- Andra, K.¹ Chakrabarti, C.² Acharya, T.³

5
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- Factoring wavelet transforms into lifting schemes
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- (1998) Journal of Fourier Anal. Appl. , vol.41 , pp. 247-269
- Daubechies, I.¹ Sweldens, W.²

6
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- A scalable and programmable architecture for 2-D DWT decoding
- Ravasi, M., Tenze, L., Mattavelli, M.: A scalable and programmable architecture for 2-D DWT decoding. IEEE Trans. on Video Tech. 12 (2002) 671-677
- (2002) IEEE Trans. on Video Tech. , vol.12 , pp. 671-677
- Ravasi, M.¹ Tenze, L.² Mattavelli, M.³

7
- 0036538167
- A VLSI architecture for lifting-based forward and inverse wavelet transform
- Andra, K., et al.: A VLSI architecture for lifting-based forward and inverse wavelet transform. IEEE Transactions on Signal Processing 50 (2002) 966-977
- (2002) IEEE Transactions on Signal Processing , vol.50 , pp. 966-977
- Andra, K.¹

8
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- A programmable parallel VLSI architecture for 2-D discrete wavelet transform
- Chen, C.Y., et al.: A programmable parallel VLSI architecture for 2-D discrete wavelet transform. Journal of VLSI Signal Processing 28 (2001) 151-163
- (2001) Journal of VLSI Signal Processing , vol.28 , pp. 151-163
- Chen, C.Y.¹

9
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- 'software-pipelined' 2-D discrete wavelet transform with VLSI hierarchical implementation
- Zhang, C., et al.: 'software-pipelined' 2-D discrete wavelet transform with VLSI hierarchical implementation. In: Proc. of RISSP '03. (2003) 148-153
- (2003) Proc. of RISSP '03 , pp. 148-153
- Zhang, C.¹

10
- 0035018998
- Analysis and architecture design of ebcot for jpeg2000
- Chen, K., Lian, C., Chen, H., Chen, L.: Analysis and architecture design of ebcot for jpeg2000. In: IEEE ISCAS. (2001) 765-768
- (2001) IEEE ISCAS , pp. 765-768
- Chen, K.¹ Lian, C.² Chen, H.³ Chen, L.⁴

11
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- A high-performance parallel mode EBCOT architecture design for JPEG2000
- Long, Y., Zhang, C., Kurdahi, F.: A high-performance parallel mode EBCOT architecture design for JPEG2000. In: Proc. IEEE SOCC. (2004) 213-216
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12
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- Efficient pass-parallel architecture for EBCOT in JPEG2000
- Chiang, J., Lin, Y., Hsieh, C.: Efficient pass-parallel architecture for EBCOT in JPEG2000. In: IEEE ISCAS. (2002) 773-776
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- Chiang, J.¹ Lin, Y.² Hsieh, C.³

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.