A lower-power register file based on complementary pass-transistor adiabatic logic

IEICE Transactions on Information and Systems

Volumn E88-D, Issue 7, 2005, Pages 1479-1485

  Hu, Jianping ^a   Xu, Tiefeng ^a   Li, Hong ^a  

^a NINGBO UNIVERSITY   (China)

Author keywords

Adiabatic logic; Low power; Register file; VLSI design

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITANCE; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; DECODING; ELECTRIC CLOCKS; ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT; TRANSISTORS; VLSI CIRCUITS;

ADIABATIC LOGIC; LOW POWER; REGISTER FILE; VLSI DESIGN;

FORMAL LOGIC;

EID: 26044463497     PISSN: 09168532     EISSN: 17451361     Source Type: Journal    
DOI: 10.1093/ietisy/e88-d.7.1479     Document Type: Article

References (15)

1. J.M. Rabaey and M. Pedram, Low power design methodologies, pp.65-95, Kluwer Academic Publishers, Boston, 1996.
2. S. Kim and M.C. Papaefthymiou, "True single-phase adiabatic circuitry," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.9, no.1, pp.52-63, Jan. 2001.
3. J. Lim, D.G. Kim, and S.I. Chae, "nMOS reversible energy recovery logic for ultra-low-energy applications," IEEE J. Solid-State Circuits, vol.35, no.6, pp.865-875, June 2000.
4. W.C. Athas, L. Svensson, J.G. Koller, N. Tzartzanis, and E.Y.C. Chou, "Low-power digital systems based on adiabatic-switching principles," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.2, no.4, pp.398-407, 1994.
5. J.P. Hu, W.J. Zhang, and Y.S. Xie, "Complementary pass-transistor adiabatic logic and sequential circuits using three-phase power supply," Proc. 47th Midwest Symposium on Circuits and Systems, vol.II, pp.201-204, Hiroshima, Japan, July 2004.
6. V.G. Oklobdzija, D. Maksimovic, and F. Lin, "Pass-transistor adiabatic logic using single power-clock supply," IEEE Trans. Circuits Syst.II, Analog Digit. Signal Process., vol.44, no. 10, pp.842-846, 1997.
7. Y. Moon and D. Jeong, "An efficient charge recovery logic circuit," IEEE J. Solid-State Circuits, vol.31, no.4, pp.514-521, 1996.
8. A. Kramer, J.S. Denker, B. Flower, and J. Moroney, "2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits," Proc. International Symposium on Low Power Electronics and Design, pp.191-196, 1995.
9. F. Liu and K. T. Lau, "Pass-transistor adiabatic logic with NMOS pull-down configuration," Electron. Lett., vol.34, no.8, pp.739-741, 1998.
10. J. Montanaro, R.T. Witek, K. Anne, A.J. Black, E.M. Cooper, D.W. Dobberpuhl, P.M. Donahue, J. Eno, G.W. Hoeppner, D. Krackemyer, T.H. Lee, P.C.M. Lin, L. Madden, D. Murray, M.H. Pearce, S. Santhanam, K.J. Snyder, R. Stephany, and S.C. Thierauf, "A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor," IEEE J. Solid-State Circuits, vol.31, no.11, pp.1703-1714, 1996.
11. Y. Moon and D. K. Jeong, "A 32 × 32-b adiabatic register file with supply clock generator," IEEE J. Solid-State Circuits, vol.33, no.5, pp.696-701, 1998.
12. K.W. Ng and K.T. Lau, "A novel adiabatic register file design," J. Circuit Syst., Comput., vol.10, no.1, pp.67-76, 2000.
13. J.H. Kwon, J. Lim, and S.I. Chae, "A three-port nRERL register file for ultra-low-energy applications," Proc. International Symposium on Low Power Electronics and Design, pp. 161-166, 2000.
14. N. Tzartzanis and W.C. Athas, "Energy recovery for the design of high-speed, low-power static RAMs," Proc. International Symposium on Low Power Electronics and Design, pp.55-60, Monterey, CA, Aug. 1996.
15. D. Maksimovic and V.G. Oklobdzija, "Integrated power clock generators for low energy logic," Proc. IEEE Power Electronics Specialists Conf., pp.61-67, Atlanta, GA, 1995.