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Volumn , Issue , 2002, Pages 133-138
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Filling the via hole of IC by VPES (vacuum printing encapsulation systems) for stacked chip (3D packaging)
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Author keywords
[No Author keywords available]
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Indexed keywords
ASPECT RATIO;
CHIP SCALE PACKAGES;
FILLING;
INTEGRATED CIRCUITS;
MODIFIED ATMOSPHERE PACKAGING;
PACKAGING;
PRINTING;
3D PACKAGING;
CONDUCTIVE PASTES;
NON CONDUCTIVE PASTES;
NONCONDUCTIVE PASTE;
PRINTING CONDITIONS;
VACUUM CONDITION;
VPES (VACUUM PRINTING ENCAPSULATION SYSTEMS);
WAFER STACKING;
ELECTRONICS PACKAGING;
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EID: 25844518945
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/EMAP.2002.1188826 Document Type: Conference Paper |
Times cited : (4)
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References (18)
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