Low-power high-speed level shifter design for block-level dynamic voltage scaling environment

2005 International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2005, Pages 229-232

  Tran, Canh Q ^a   Kawaguchi, Hiroshi ^a   Sakurai, Takayasu ^a  

^a INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION;

BYPASSING ENABLED LEVEL SHIFTERS (BELS); CONTENTION MITIGATED LEVEL SHIFTERS (CMLS); POWER DELAYS; VOLTAGE SCALING;

INTEGRATED CIRCUIT LAYOUT;

EID: 25844497542     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icicdt.2005.1502637     Document Type: Conference Paper

References (4)

1. TH FD-SOI Technology," ISSCC, pp. 106-107,Feb. 2003.
2. J. S. Shor, Y. Afek, and E. Engel, "IO buffer for high performance, low-power application," CICC, pp. 595-598, May 1997.
3. R. Puri, L. Stok, J. Cohn, D. Kung, D. Pan, D. Sylvester, A. Srivastava, and S. Kulkami, "Pushing ASIC Performance in a Power Envelope," DAC, pp. 788-793, June 2003.
4. http://www-device.eecs.berkeley.edu/~ptm/