RC hardened FPGA configuration SRAM cell design

Electronics Letters

Volumn 40, Issue 9, 2004, Pages 525-526

  Wang, W ^a  

^a University of Wisconsin Milwaukee   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ENERGY TRANSFER; FIELD PROGRAMMABLE GATE ARRAYS; RESISTORS; SILICON; TRANSISTORS; WEBSITES;

DUAL INTERLOCKED CELL; RESISTOR DECOUPLING TECHNIQUE; SHRUNK TECHNOLOGY;

STATIC RANDOM ACCESS STORAGE;

EID: 2542474434     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20040360     Document Type: Article

References (2)

1. Calin, T., Nicolaidis, M., and Velazco, R.: 'Upset hardened memory design for submicron CMOS technology', IEEE Trans. Nucl. Sci., 1996, 43, (6), pp. 2874-2878
2. Wang, J.J., et al.: 'SRAM based re-programmable FPGA for space application', IEEE Trans. Nucl. Sci., 1999, 46, (6), pp. 1728-1735