A 3.5-GHz PLL for fast low-IF/zero-IF LO switching in an 802.11 transceiver

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 9, 2005, Pages 1909-1920

  Gierkink, Sander L J ^a,b   Li, Dandan ^a,c   Frye, Robert C ^a,d   Boccuzzi, Vito ^b,e  

^a AGERE SYSTEMS   (United States)

^b Conexant Systems ^*  (United States)

^c BROADCOM CORPORATION   (United States)

^d RF Design Consulting LLC   (United States)

^e Analog Devices ^*

Author keywords

Frequency synthesizers; Phase locked loops; Voltage controlled oscillators

Indexed keywords

BANDWIDTH; FREQUENCIES; FREQUENCY SYNTHESIZERS; OSCILLATORS (ELECTRONIC); SWITCHING; VARIABLE FREQUENCY OSCILLATORS;

LOCAL OSCILLATOR (LO) FREQUENCY; LOOP BANDWIDTH; PHASE-FREQUENCY DETECTORS (PFD); PHASED-LOCKED LOOPS;

TRANSCEIVERS;

EID: 25144505696     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.848175     Document Type: Conference Paper

References (12)

1. A. M. Fahim and M. I. Elmasry, "A fast lock digital phase-locked-loop architecture for wireless applications," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 2, pp. 63-72, Feb. 2003.
2. M. Keaveney, P. Walsh, M. Tuthill, C. Lyden, and B. Hunt, "A 10 μs fast switching PLL synthesizer for a GSM/EDGE base-station," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, vol. 1, 2004, pp. 192-193.
3. C. Vaucher, "An adaptive PLL tuning system architecture combining high spectral purity and fast settling time," IEEE J. Solid-State Circuits, vol. 35, no. 4, pp. 490-502, Apr. 2000.
4. B. Zhang and P. Allen, "Feed-forward compensated high switching speed digital phase-locked loop frequency synthesizer," in Proc. IEEE Int. Symp. Cirscuits and Systems (ISCAS), vol. 4, 1999, pp. 371-374.
5. C.-W. Lo and H. C. Luong, "A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications," IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 459-470, Apr. 2002.
6. S. Levantino, C. Samori, A. Bonfanti, S. Gierkink, A. Lacaita, and V. Boccuzzi, "Frequency dependence on bias current in 5-GHz CMOS VCOs: Impact on tuning range and flicker noise up-conversion," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1003-1011, Aug. 2002.
7. E. Hegazi and A. A. Abidi, "Varactor characteristics, oscillator tuning curves, and AM-FM conversion," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1033-1039, Jun. 2003.
8. S. L. J. Gierkink and E. van Tuijl, "A coupled sawtooth oscillator combining low jitter with high control linearity," IEEE J. Solid-State Circuits, vol. 37, no. 6, pp. 702-710, Jun. 2002.
9. S. L. J. Gierkink, D. Li, R. C. Frye, and V. Boccuzzi, "A 3.5 GHz integer-N PLL with dual on-chip loop filters and VCO tune ports for fast low-IF/zero-IF LO switching in an 802.11 transceiver," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Oct. 2004, pp. 629-632.
10. S. L. J. Gierkink, R. C. Frye, and V. Boccuzzi, "Differentially "bathtub"-tuned CMOS VCO using inductively coupled varactors," in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2003, pp. 501-504.
11. E. Hegazi, H. Sjöland, and A. A. Abidi, "A filtering technique to lower LC oscillator phase noise," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1921-1930, Dec. 2001.
12. S. Kapur and D. E. Long, "IES3: Efficient electrostatic and electromagnetic simulation," IEEE Comput. Sci. Eng., vol. 5, no. 4, pp. 60-67, Oct.-Dec. 1998.