Lean power management technique: The lowest power consumption for the given operating speed of LSIs

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1997, Pages 99-100

  Sakiyama, Shiro ^a   Nakahira, Hiroyuki ^a   Fukuda, Masaru ^a   Yamamoto, Akira ^a   Kinoshita, Masayoshi ^a   Matsuzawa, Akira ^a   Yamamoto, Hiroo ^a   Kato, Yoshiaki ^a   Matsuya, Yasuyuki ^a   Mutoh, Shin'ichiro ^a   Fukuda, Hideki ^a   Nishino, Yutaka ^a   Sakurai, Tetsuma ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING;

INTERNAL LOWEST VOLTAGE DETECTOR (ILVD); POWER MANAGEMENT TECHNIQUE; VARIABLE DELAY MODULE (VDM);

LSI CIRCUITS;

EID: 0031356849     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)