A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 414-415+409

  Rogenmoser, Robert ^a   O'Donnell, Lief ^a   Nishimoto, Steve ^a  

^a BROADCOM CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; ROM; TRANSISTORS;

FLOATING-POINT COPROCESSORS;

MICROPROCESSOR CHIPS;

EID: 0036116902     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. A 1 GHz power efficient single chip multiprocessor system for broadband networking applications