Adaptive supply voltage technique for low swing interconnects

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2004, Pages 284-287

  Jeong, Woopyo ^a   Paul, Bipul Chandra ^a   Roy, Kaushik ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; ENERGY UTILIZATION; POWER CONTROL;

COMPLEXITY OF CIRCUIT; MULTIPLEXER ARCHITECTURE; MULTIPLEXER DELAY; NOVEL DESIGN STRATEGY;

INTERCONNECTION NETWORKS;

EID: 2442609811     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. H. B. Bakoglu, Circuits, Interconnect and Packaging for VLSI, Addison-Wesley, 1990.
2. A. Chandrakasan, et al., Design of High-Performance Microprocessor Circuits, IEEE press, 1999.
3. D. Sylvester and K. Keutzer, "Getting to the bottom of deep submicron II: A global wiring paradigm," proc. DAC, pp. 726-731, 1998.
4. D. Liu, et al., "Power consumption estimation in CMOS VLSI chips," IEEE J. Solid-State Circuits, vol. 29, pp. 663-670, June 1994.
5. Hui Zhang, et al., "Low-Swing On-Chip Signaling Techniques: Effectiveness and Robustness," IEEE Trans. On VLSI Systems, vol. 8, no. 3, Jun. 2000.
6. Yoshinobu Nakagome, et al, "Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's," IEEE Trans. of Solid-State Circuits, vol. 28, no. 4, April 1993.
7. Mitsuru Hiraki, et al., "Data-Dependent Logic Swing Internal Bus Architecture for Ultralow-Power LSI's," IEEE J. of Solid-State Circuits, vol. 30, no. 4, Apr. 1995